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VLSI Engineer | Digital Design & Verification | MS Dhoni & F1 Fan ๐๐๏ธ
Coding for 5 years.
Contribution Graph
Activity Timeline
Commits and contributions grouped by day, week, or month.
Pushed to main at mannraval1/HDLBits-Solutions
February 2nd, 2026 5:48 AM
Starred bhattiabdulrehman235-blip/Risc-V-3-Stage-Pipelined-Architecture-System-Verilog-Implementation
January 30th, 2026 7:00 PM
Starred bhattiabdulrehman235-blip/Risc-V-Pipelined-Architecture-System-Verilog-Implementation-With-CSR
January 30th, 2026 7:00 PM
Starred riscv/learn
January 30th, 2026 8:02 AM
Pushed to main at mannraval1/Sync-FIFO
January 27th, 2026 4:29 AM
Created branch main in mannraval1/Sync-FIFO
January 27th, 2026 4:28 AM
Pushed to main at mannraval1/HDLBits-Solutions
January 24th, 2026 7:53 AM
Pushed to main at mannraval1/HDLBits-Solutions
January 24th, 2026 7:42 AM
Starred jhshi/openofdm
January 24th, 2026 12:35 AM
Pushed to main at mannraval1/Machine-to-Machine-Communication
January 22nd, 2026 6:25 PM