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SystemRDL
/
PeakRDL-regblock
Public
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
GNU Lesser General Public License v3.0
Updated Jan 8, 2026
Created Nov 11, 2020
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74
stars
55
forks
17
watchers
16
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Repository Complexity
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Files
-
Size (KB)
1,097
Issues & Activity
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Open Issues 10
Closed Issues 90
Open Issues
100
Activity Peak
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Feb 5, 2026 • 1 events
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