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Evensgn
/
RISC-V-CPU
Public
RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
Updated Feb 5, 2026
Created Dec 6, 2017
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344
stars
48
forks
2
watchers
1
open issues
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Top Contributors
EV
Evensgn
101 commits
Recent Stargazers
EN
Engineev
about 8 years ago
WO
woshiyyya
about 8 years ago
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Michaelvll
about 8 years ago
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chrsw
almost 8 years ago
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lbuchli
over 7 years ago
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yybbest
over 7 years ago
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laonahongchen
about 7 years ago
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dengwxn
about 7 years ago
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baixinz
about 7 years ago
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xiaoxiaohuixxh
almost 7 years ago
Repository Complexity
Approximate file count and repository size.
Files
-
Size (KB)
5,632
Issues & Activity
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Open Issues 1
Closed Issues 0
Open Issues
1
Activity Peak
Most recent day with highest activity
Feb 5, 2026 • 1 events
Stars & Forks Over Time
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